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w25P80 and w25p16 publication release date: september 22, 2006 - 1 - revision l 8m-bit and 16m-bit serial flash memory formally nexflash nx25P80 and nx25p16 the winbond w25P80/16 are fully compatible with the previous nexflash nx25P80/16 serial flash memories. www.datasheet.co.kr datasheet pdf - http://www..net/
w25P80 and w25p16 - 2 - table of contents- 1. general des cription ......................................................................................................... 4 2. featur es ...................................................................................................................... .......... 4 3. pin configurati on 208-mil................................................................................................. 5 4. pin descriptio n 208-mi l ...................................................................................................... 5 5. pin configurati on 300-mil................................................................................................. 6 6. pin descriptio n 300-mi l ...................................................................................................... 6 6.1 package ty pes ............................................................................................................... 7 6.2 chip select (/cs) ............................................................................................................ 7 6.3 serial data ou tput (do) ................................................................................................. 7 6.4 write protec t (/wp)......................................................................................................... 7 6.5 hold (/ho ld) ............................................................................................................... 7 6.6 serial clo ck (clk) .......................................................................................................... 7 6.7 serial data input (d i) ...................................................................................................... 7 7. block di agram .................................................................................................................. .... 8 8. functional des cription ................................................................................................... 9 8.1 spi operat ions ......................................................................................................... 9 8.1.1 spi m odes ...................................................................................................................... ..9 8.1.2 hold func tion.................................................................................................................9 8.2 write prot ection.................................................................................................... 9 8.2.1 write protect featur es......................................................................................................9 9. control and status registers................................................................................... 10 9.1 status register .................................................................................................... 10 9.1.1 busy........................................................................................................................... ...10 9.1.2 write enable lat ch (wel ) ..............................................................................................10 9.1.3 block protect bits (bp2, bp1, bp0)................................................................................11 9.1.4 reserved bits .................................................................................................................1 1 9.1.5 status register protect (s rp)........................................................................................11 9.1.6 status register me mory prot ection ................................................................................12 9.2 instructio ns........................................................................................................... 13 9.2.1 manufacturer and device identific ation ..........................................................................13 9.2.2 instruction set (1) .............................................................................................................14 9.2.3 write enabl e (06h) ..........................................................................................................15 9.2.4 read status regi ster ( 05h) ............................................................................................ 16 9.2.5 write status r egister (01h) ............................................................................................17 9.2.6 read data (03h) .............................................................................................................18 9.2.7 fast read (0bh) .............................................................................................................19 www.datasheet.co.kr datasheet pdf - http://www..net/
w25P80 and w25p16 publication release date: september 22, 2006 - 3 - revision l 9.2.8 page program (02h) .......................................................................................................20 9.2.9 sector eras e (d8h) .........................................................................................................21 9.2.10 chip eras e (c7h) ..........................................................................................................22 9.2.11 power-down (b9h) ........................................................................................................23 9.2.12 release power-down / de vice id (abh) .......................................................................23 9.2.13 read manufacturer / de vice id (90h) ...........................................................................25 9.2.14 jedec id (9fh) ...........................................................................................................26 9.2.15 read parameter page ( 53h) ........................................................................................ 27 9.2.16 fast read paramete r page (5 bh) ................................................................................28 9.2.17 program paramete r page ( 52h) ................................................................................... 29 9.2.18 erase paramete r page (d 5h) ....................................................................................... 31 10. electrical chara cteristi cs......................................................................................... 32 10.1 absolute maximum ratings (1) .................................................................................... 32 10.2 operating ranges ......................................................................................................... 32 10.3 power-up timing and write inhibit thre shold .............................................................. 33 10.4 dc electrical characteristics (preliminary) (1) .............................................................. 34 10.5 ac measurement conditi ons........................................................................................ 35 10.6 ac electrical c haracterist ics ........................................................................................ 36 10.7 serial output timi ng ..................................................................................................... 38 10.8 input ti ming .................................................................................................................. 3 8 10.9 hold ti ming................................................................................................................... 3 8 11. package specific ation .................................................................................................... 39 11.1 8-pin soic 208-mil (winbond package code ss) ....................................................... 39 11.2 16-pin soic 300-mil (wi nbond package c ode sf)..................................................... 40 12. ordering info rmation .................................................................................................... 41 13. revision history ............................................................................................................... .42 www.datasheet.co.kr datasheet pdf - http://www..net/
w25P80 and w25p16 - 4 - 1. general description the w25P80 (8m-bit) and w25p16 (16m-bit) serial flash memories provide a storage solution for systems with limited space, pins and power. they are ideal for code download applications as well as storing voice, text and data. the devices operate on a single 2.7v to 3.6v power supply with current consumption as low as 4ma active and 1a for pow er-down. devices are offered in space-saving soic packages. as part of a family of serial fl ash products, winbond also offers compatible devices in 1m/2m/4m-bit densities. the w25P80/16 array is organized into 4,096/8,192 programmable pages of 256-bytes each. up to 256 bytes can be programmed at a time using the page program instruction. pages are grouped into 16/32 erasable sectors of 256 pages (64k-byte) each as shown in figure 2. both sector erase and chip (full chip) erase instructions are supported. additionally, a 256-byte parameter page is provided for user data that is typically stored in eeproms such as id or revision numbers and configuration parameters. the parameter page is separate from t he main array allowing for much faster erase times. the serial peripheral interface (spi) consists of four pins (serial clock, chip select, serial data in and serial data out) that support high speed serial data transfers up to 50mhz. a hold pin, write protect pin and programmable write pr otect features provide further c ontrol flexibility. additionally, the device can be queried for manufacturer and device type. the winbond w25P80/16 are fully compatible with t he previous nexflash nx25P80/16 serial flash memories. 2. featur es ? 8m / 16m / 32m-bit serial flash memories ? family of serial flash memories ? w25P80: 8m-bit/1m-byte (1,048,576) ? w25p16: 16m-bit/2m-byte (2,097,152) ? 256-bytes per programmable page ? compatible 1m/2m/4m-bit devices ? 4-pin spi serial interface ? clock, chip select, data in, data out ? easily interfaces to popular microcontrollers ? compatible with spi modes 0 and 3 ? optional hold function for spi flexibility ? low power consumption, wide temperature range ? single 2.7 to 3.6v supply ? 4ma active current, 1a power-down (typ) ? -40 to +85c operating range ? fast and flexible serial data access ? clock operation to 50mhz ? auto-increment read capability ? manufacturer and device type id ? programming features ? page program up to 256 bytes in 3.5ms ? sector erase (64k-byte) 0.6 seconds ? 100,000 erase/write cycles ? twenty-year data retention ? software and hardware write protection ? write-protect all or portion of memory ? enable/disable protection with /wp pin ? parameter page ? 256 byte page for id# revision# or configuration data ? separate from array, erase time <200ms ? space saving packaging ? 8-pin soic (w25P80 and w25p16) ? 16-pin soic (w25p16) ? ideal for systems with limited pins, space, and power ? controller-based serial code-download ? c systems storing data, text or voice ? battery-operated and portable products www.datasheet.co.kr datasheet pdf - http://www..net/
w25P80 and w25p16 publication release date: september 22, 2006 - 5 - revision l 3. pin configuration 208-mil figure 1a. w25P80/16 pin assi gnments, 8-pin soic 208-mi 4. pin description 208-mil pin no. pin name i/o function 1 /cs i chip select input 2 do o data output 3 /wp i write protect input 4 gnd ground 5 di i data input 6 clk i serial clock input 7 /hold i hold input 8 vcc power supply www.datasheet.co.kr datasheet pdf - http://www..net/
w25P80 and w25p16 - 6 - 5. pin configuration 300-mil figure 1b. w25p16 pin assignments, 16-pin soic 300-mil 6. pin description 300-mil pad no. pad name i/o function 1 /hold i hold input 2 vcc power supply 3 n/c no connect 4 n/c no connect 5 n/c no connect 6 n/c no connect 7 /cs i chip select input 8 do o data output 9 /wp i write protect input 10 gnd ground 11 n/c no connect 12 n/c no connect 13 n/c no connect 14 n/c no connect 15 di i data input 16 clk i serial clock input www.datasheet.co.kr datasheet pdf - http://www..net/
w25P80 and w25p16 publication release date: september 22, 2006 - 7 - revision l 6.1 package types the w25P80/16 are primarily offered in soic packages. the w25P80 and w25p16 use an 8-pin plastic 208-mil width soic (winbond package code ss) (nexflash package code s) and the w25p16 also uses a 16-pin plastic 300-mil width so ic (winbond package code sf) (nexflash package code f) as shown in figures 1a and 1b respectively . package diagrams and dimensions are illustrated at the end of this data sheet. optional 8-contact ml p packages may be available. please contact winbond for further mlp package information. 6.2 chip select (/cs) the spi chip select (/cs) pin enables and disables device operation. when /cs is high the device is deselected and the serial data output (do) pin is at high impedance. when deselected, the devices power consumption will be at standby levels unless an in ternal erase, program or status register cycle is in progress. when /cs is brought low the device will be select ed, power consumption will increase to active levels and instructions can be writt en to and data read from the device. after power-up, /cs must transition from high to low before a new instruction will be accepted. the /cs input must track the vcc supply level at power-up (see ?write pr otection? and figure 16). if needed a pull-up resister on /cs can be used to accomplish this. 6.3 serial data output (do) the spi serial data output (do) pin provides a means for data and status to be serially read from (shifted out of) the device. data is shifted out on the falling edge of the serial clock (clk) input pin. 6.4 write protect (/wp) the write protect (/wp) pin can be used to prevent the status register from being written. used in conjunction with the status register?s block pr otect (bp2, bp1, and bp0) bits and status register protect (srp) bits, a portion or the entire memory array can be hardware protected. the /wp pin is active low. 6.5 hold (/hold) the /hold pin allows the device to be paused while it is actively selected. when /hold is brought low, while /cs is low, the do pin will be at high impedanc e and signals on the di and clk pins will be ignored (don?t care). when /hold is brought high, device operation can resume. the /hold function can be useful when multiple devices are shari ng the same spi signals. (?see hold function?) 6.6 serial clock (clk) the spi serial clock input (clk) pin provides t he timing for serial input and output operations. ("see spi "operations") 6.7 serial data input (di) the spi serial data input (di) pin provides a m eans for instructions, addresses and data to be serially written to (shifted into) the device. data is latc hed on the rising edge of the se rial clock (clk) input pin. www.datasheet.co.kr datasheet pdf - http://www..net/
w25P80 and w25p16 - 8 - 7. block diagram figure 2. w25P80 and w25p16 block diagram www.datasheet.co.kr datasheet pdf - http://www..net/
w25P80 and w25p16 publication release date: september 22, 2006 - 9 - revision l 8. functional description 8.1 spi operations 8.1.1 spi modes the w25P80/16 is accessed through an spi compatible bus consisting of four signals: serial clock (clk), chip select (/cs), serial data input (di) and serial data output (do). both spi bus operation modes 0 (0,0) and 3 (1,1) are supported. the primary difference between mode 0 and mode 3 concerns the normal state of the clk signal when the spi bus master is in standby and data is not being transferred to the serial flash. for mode 0 t he clk signal is normally low. for mode 3 the clk signal is normally high. in either case data input on the di pin is sampled on the rising edge of the clk. data output on the do pin is clocked out on the falling edge of clk. 8.1.2 hold function the /hold signal allows the w25P80/16 operation to be paused while it is actively selected (when /cs is low). the /hold function may be useful in cases w here the spi data and clock signals are shared with other devices. for example, consider if the page buffer was only partially written when a priority interrupt requires use of the spi bus. in this case the /hold function can save the state of the instruction and the data in the buffer so programmi ng can resume where it left off once the bus is available again. to initiate a /hold condition, the device must be selected with /cs low. a /hold condition will activate on the falling edge of the /hold signal if t he clk signal is already low. if the clk is not already low the /hold condition will activate after the next falling edge of clk. the /hold condition will terminate on the rising edge of the /hold signal if the clk signal is already low. if the clk is not already low the /hold condition will terminate after the next falling edge of clk. during a /hold condition, the serial data output (do) is high impedance, and serial data input (di) and serial clock (clk) are ignored. the chip select (/cs) signal should be kept active (low) for the full duration of the /hold operation to avoid resetting the inte rnal logic state of the device. 8.2 write protection applications that use non-volatile memory must ta ke into consideration the possibility of noise and other adverse system conditions that may compromi se data integrity. to address this concern the w25P80/16 provides several means to pr otect data from inadvertent writes. 8.2.1 write protect features ? device resets when vcc is below threshold. ? time delay write disable after power-up. ? write enable/disable instructions. ? automatic write disable after program and erase. ? software write protection using status register. ? hardware write protection using status register and /wp pin. ? write protection using power-down instruction. www.datasheet.co.kr datasheet pdf - http://www..net/
w25P80 and w25p16 - 10 - upon power-up or at power-down the w25P80/16 will maintain a reset condition while vcc is below the threshold value of v wi , (see power-up timing and voltage levels and figure 17). while reset, all operations are disabled and no instructions are recognized. during power-up and after the vcc voltage exceeds v wi , all program and erase related instructions are further disabled for a time delay of t puw . this includes the write enable, page program, se ctor erase, chip erase and the write status register instructions. note that the chip select pin (/cs) must tr ack the vcc supply level at power-up until the vcc-min level and t vsl time delay is reached. if needed a pull-up resister on /cs can be used to accomplish this. after power-up the device is automatically placed in a write-disabled state with the status register write enable latch (wel) set to a 0. a write enable instruction must be issued before a page program, sector erase, chip erase or write stat us register instruction will be accepted. after completing a program, erase or write instruction the write enable latch (we l) is automatically cleared to a write-disabled state of 0. software controlled write protection is facilitated using the write stat us register instruction and setting the status register protect (srp ) and block protect (bp2, bp1, and bp0 ) bits. these status register bits allow a portion or all of the memory to be c onfigured as read only. used in conjunction with the write protect (/wp) pin, changes to the status register can be enabled or disabled under hardware control. see status register for further information. additionally, the power-down instruction offers an extra level of write protection as all instructions are ignored except for the releas e power-down instruction. 9. control and status registers the read status register instruction can be used to provide status on the av ailability of the flash memory array, if the device is write enabled or dis abled, and the state of writ e protection. the write status register instruction can be used to configure the devices wr ite protection features. see figure 3. 9.1 status register 9.1.1 busy busy is a read only bit in the status register (s0) t hat is set to a 1 state w hen the device is executing a page program, sector erase, chip erase or write st atus register instructi on. during this time the device will ignore further instruct ions except for the read status register instruction (see t w , t pp , t se and t ce in ac characteristics). when the program, eras e or write status regi ster instruction has completed, the busy bit will be cleared to a 0 st ate indicating the device is ready for further instructions. 9.1.2 write enable latch (wel) write enable latch (wel) is a read only bit in the status register (s1) that is set to a 1 after executing a write enable instruction. the we l status bit is cleared to a 0 w hen the device is write disabled. a write disable state occurs upon power-up or after any of the following instructi ons: write disable, page program, sector erase, chip er ase and write status register. www.datasheet.co.kr datasheet pdf - http://www..net/
w25P80 and w25p16 publication release date: september 22, 2006 - 11 - revision l 9.1.3 block protect bits (bp2, bp1, bp0) the block protect bits (bp2, bp1, bp0 ) are non-volatile read/write bits in the status register (s4, s3, s2) that provide write protection control and status. block protect bits can be set using the write status register instruction (see t w in ac characteristics). all, none or a portion of the memory array can be protected from program and erase instructions (see status register memory protection table). the factory default setting for the block protection bi ts is 0, none of the array protected. the block protect bits can not be written to if the status r egister protect (srp) bit is set to 1 and the write protect (/wp) pin is low. 9.1.4 reserved bits status register bit locations 5 and 6 are reserved fo r future use. current devices will read 0 for these bit locations. it is recommended to mask out the rese rved bit when testing the status register. doing this will ensure compatibilit y with future devices. 9.1.5 status register protect (srp) the status register protect (srp) bit is a non-volatile read/write bit in the status regist er (s7) that can be used in conjunc tion with the write protect (/wp) pin to disable writes to the status register. when t he srp bit is set to a 0 state (factory default) the /wp pin has no control over the status register. w hen the srp pin is set to a 1, the write status register instruction is locked out while the /wp pin is low. when the /wp pin is high the write status register instruction is allowed. figure 3. status register bit locations www.datasheet.co.kr datasheet pdf - http://www..net/
w25P80 and w25p16 - 12 - 9.1.6 status register memory protection status register(1) w25p16 (16m-bit) memory protection bp2 bp1 bp0 sector(s) addr esses density (kb) portion 0 0 0 none none none none 0 0 1 31 1f0000h - 1fffffh 512k-bit upper 1/32 0 1 0 30 and 31 1e0000h - 1fffffh 1m-bit upper 1/16 0 1 1 28 thru 31 1c0000h - 1fffffh 2m-bit upper 1/8 1 0 0 24 thru 31 180000h - 1fffffh 4m-bit upper 1/4 1 0 1 16 thru 31 100000h - 1fffffh 8m-bit upper 1/2 1 1 x all 000000h - 1fffffh all memory plus parameter page status register(1) w25P80 (8m-bit) memory protection bp2 bp1 bp0 sector(s) addr esses density (kb) portion 0 0 0 none none none none 0 0 1 15 0f0000h - 0fffffh 512k-bit upper 1/16 0 1 0 14 and 15 0e0000h - 0fffffh 1m-bit upper 1/8 0 1 1 12 thru 15 0c0000h - 0fffffh 2m-bit upper 1/4 1 0 0 8 thru 15 080000h - 0fffffh 4m-bit upper 1/2 1 0 1 all 000000h - 0fffffh 1 1 x all 000000h - 0fffffh all memory plus parameter page note: 1. x = don?t care www.datasheet.co.kr datasheet pdf - http://www..net/
w25P80 and w25p16 publication release date: september 22, 2006 - 13 - revision l 9.2 instructions the instruction set of the w25P80/16 consists of th irteen basic instructions that are fully controlled through the spi bus (see instruction set table). instru ctions are initiated with the falling edge of chip select (/cs). the first byte of data clocked into t he di input provides the in struction code. data on the di input is sampled on the rising edge of clo ck with most significant bit (msb) first. instructions vary in length from a single byte to several bytes and may be followed by address bytes, data bytes, dummy bytes (don?t care), and in some ca ses, a combination. inst ructions are completed with the rising edge of edge /cs. clock relative ti ming diagrams for each instruction are included in figures 4 through 21. all read instructions can be completed after any clocked bit. however, all instructions that write, program or erase must complete on a byte boundary (/cs driven high after a full 8-bits have been clocked) otherwise the instructi on will be terminated. this feature further protects the device from inadvertent writes . additionally, while the memory is being programmed or erased, or when the status register is being written, all inst ructions except for read status register will be ignored until the program or erase cycle has completed. 9.2.1 manufacturer and device identification manufacturer id (m7-m0) winbond serial flash efh device id (id7-id0) (id15-id0) instruction abh, 90h 9fh w25P80 13h 2014h w25p16 14h 2015h www.datasheet.co.kr datasheet pdf - http://www..net/
w25P80 and w25p16 - 14 - 9.2.2 instruction set (1) instruction name byte 1 code byte 2 (5) byte 3 byte 4 byte 5 byte 6 n-bytes write enable 06h write disable 04h read status register 05h (s7?s0) (1) (2) write status register 01h s7?s0 read data 03h a23?a16 a15?a8 a7?a0 (d7?d0) (next byte) continuous fast read 0bh a23?a16 a15?a8 a7?a0 dummy (d7?d0) (next byte) continuous page program 02h a23?a16 a15?a8 a7?a0 (3) (d7?d0) (next byte) up to 256 bytes (128 words) (3) sector erase d8h a23?a16 a15?a8 a7?a0 chip erase c7h power-down b9h read parameter page 53h don?t care don?t care a7?a0 d7-d0 next byte next byte fast read parameter page 5bh don?t care don?t care a7?a0 dummy d7-d0 next byte program parameter page 52h don?t care don?t care a7?a0 (3) d7-d0 d15-d8 up to 256 bytes (128 words) erase parameter page d5h release power- down / device id (4) abh dummy dummy dummy (id7-id0) (5) manufacturer/ device id (4) 90h dummy dummy 00h (m7-m0) (id7-id0) jedec id 9fh (m7-m0) manufacturer (id15-id8) memory type (id7-id0) capacity notes: 1. data bytes are shifted with most si gnificant bit first. byte fields with data in parenthesis ?( )? indicate data being read from the device on the do pin. 2. the status register content s will repeat continuously until //cs terminates the instruction. 3. the page program instruction progr ams in increments of one word (two bytes) at a time. the program address a23-a16 must be an ?even? address (a0 must equal 0). 4. see manufacturer and device identification table for device id information 5. the device id will repeat continuously until //cs terminates the instruction. www.datasheet.co.kr datasheet pdf - http://www..net/
w25P80 and w25p16 publication release date: september 22, 2006 - 15 - revision l 9.2.3 write enable (06h) the write enable instruction (figure 4) sets the write enable latch (wel) bit in the status register to a 1. the wel bit must be set prior to every page pr ogram, sector erase, chip erase and write status register instruction. the write e nable instruction is entered by drivi ng /cs low, shifting the instruction code ?06h? into the data input (di) pin on t he rising edge of clk, and then driving /cs high. figure 4. write enable instruction sequence diagram 9.2.4 write disable (04h) the write disable instruction (figure 5) resets the write enable latch (wel) bit in the status register to a 0. the write disable instruction is entered by driving /cs low, shifting the instruction code ?04h? into the di pin and then driving /cs high. note that the wel bit is automatically reset after power-up and upon completion of the write status register , page program, sector erase, and chip erase instructions. figure 5. write disable in struction sequence diagram www.datasheet.co.kr datasheet pdf - http://www..net/
w25P80 and w25p16 - 16 - 9.2.5 read status register (05h) the read status register instructi on allows the 8-bit status register to be read. the instruction is entered by driving /cs low and shifting the instructi on code ?05h? into the di pin on the rising edge of clk. the status register bits ar e then shifted out on the do pin at the falling edge of clk with most significant bit (msb) first as shown in figure 6. the status register bits are shown in figure 3 and include the busy, wel, bp2-bp0, and srp bits (see descr iption of the status register earlier in this data sheet). the status register instruction may be used at any time, even while a program, erase or write status register cycle is in progress. this allows the busy status bit to be checked to determine when the cycle is complete and if the device can accept anot her instruction. the stat us register can be read continuously, as shown in figure 6. the inst ruction is completed by driving /cs high. figure 6. read status register instruction sequence diagram www.datasheet.co.kr datasheet pdf - http://www..net/
w25P80 and w25p16 publication release date: september 22, 2006 - 17 - revision l 9.2.6 write status register (01h) the write status register instruction allows t he status register to be written. a write enable instruction must previously have been executed for the device to acc ept the write status register instruction (status register bit wel must equal 1) . once write enabled, the in struction is entered by driving /cs low, sending the instruction code ?01h?, and then writing the status register data byte as illustrated in figure 7. the status register bits are shown in figure 3 and described earlier in this data sheet. only non-volatile status register bits srp, bp2, bp1 and bp0 (bits 7, 4, 3 and 2) can be written to. all other status register bit locations are r ead-only and will not be affected by the write status register instruction. the /cs pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the write status register inst ruction will not be executed. after /cs is driven high, the self-timed write status register cycle will commence for a time duration of t w (see ac characteristics). while the write status register cycle is in progress, the read status regi ster instruction may still accessed to check the status of the busy bit. the busy bit is a 1 during the write status register cycle and a 0 when the cycle is finished and ready to accept ot her instructions again. a fter the write register cycle has finished the write enable latch (wel) bit in the status register will be cleared to 0. the write status register instru ction allows the block protect bits (bp2, bp1 and bp0) to be set for protecting all, a portion, or none of the memory fr om erase and program instructions. protected areas become read-only (see status register memory pr otection table). the write status register instruction also allows the status register protect bit (srp) to be set. this bit is used in conjunction with the write protect (/wp) pin to disable writes to the status register. when the srp bit is set to a 0 state (factory default) the /wp pin has no control over the status regi ster. when the srp pin is set to a 1, the write status register inst ruction is locked out while the /wp pin is low. when the /wp pin is high the write status register instruction is allowed. figure 7. write status register instruction sequence diagram www.datasheet.co.kr datasheet pdf - http://www..net/
w25P80 and w25p16 - 18 - 9.2.7 read data (03h) the read data instruction allows one more data by tes to be sequentially read from the memory. the instruction is initiated by driving the /cs pin lo w and then shifting the instruction code ?03h? followed by a 24-bit address (a23-a0) into the di pin. the code and address bits are latched on the rising edge of the clk pin. after the address is received, t he data byte of the addressed memory location will be shifted out on the do pin at the falling edge of clk wi th most significant bit (msb) first. the address is automatically incremented to the nex t higher address after each byte of data is shifted out allowing for a continuous stream of data. th is means that the entire memory can be accessed with a single instruction as long as the clock continues. the inst ruction is completed by driving /cs high. the read data instruction sequence is shown in figure 8. if a read data instruction is issued while an erase, program or write cycle is in process (busy=1) t he instruction is ignored and will not have any effects on the current cycle. the read data instruction allows clock rates from d.c. to a maximum of f r ( see ac electrical characteristics). figure 8. read data instruction sequence diagram www.datasheet.co.kr datasheet pdf - http://www..net/
w25P80 and w25p16 publication release date: september 22, 2006 - 19 - revision l 9.2.8 fast read (0bh) the fast read instruction is similar to the read da ta instruction except t hat it can operate at the highest possible frequency of f r (see ac electrical characteristi cs). this is accomplished by adding a ?dummy? byte after the 24-bit address as shown in figure 9. the dummy byte allows the devices internal circuits additional time for setting up the in itial address. the dummy byte data value on the di pin is a ?don?t care?. figure 9. fast read instruction sequence diagram www.datasheet.co.kr datasheet pdf - http://www..net/
w25P80 and w25p16 - 20 - 9.2.9 page program (02h) the page program instruction allows up to 256 byte s of data to be programmed at previously erased to all 1s (ffh) memory locations. a write enable instruction must be exec uted before the device will accept the page program instruction (status regi ster bit wel must equal 1). the instruction is initiated by driving the /cs pin low then shifting the instruction code ?02h? followed by a 24-bit address (a23-a0) and at least two data bytes, into the di pin. because the w25P80/16 programs in increments of one word (two bytes) at a time the 24-bi t address (a23-a0) must be an even address (a0 must equal 0). the /cs pin must be held low for the entire length of the instruction while data is being sent to the device. the page program instru ction sequence is shown in figure 10. if an entire 256 byte page is to be programmed, the la st address byte (the 8 least significant address bits) should be set to 0. if the last address byte is not zero, and the number of clocks exceed the remaining page length, the addressing will wrap to the beginning of the page. less than 256 bytes can be programmed without having any e ffect on other bytes within the same page. if more than 256 bytes are sent to the device the addressing will wrap to the beginning of the page and overwrite previously sent data. as with the write and erase instructions, the /cs pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the page pr ogram instruction will not be executed. after /cs is driven high, the self-timed page program instruction will commence for a time duration of tpp (see ac characteristics). while the page program cycl e is in progress, the read status register instruction may still be accessed for checking the st atus of the busy bit. the busy bit is a 1 during the page program cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. after t he page program cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. the p age program instruction w ill not be executed if the addressed page is protected by the block protect ( bp2, bp1, bp0) bits (see status register memory protection table). figure 10. page program instruction sequence diagram www.datasheet.co.kr datasheet pdf - http://www..net/
w25P80 and w25p16 publication release date: september 22, 2006 - 21 - revision l 9.2.10 sector erase (d8h) the sector erase instruction sets all memory within a specified sector to the erased state of all 1s (ffh). a write enable instruction must be execut ed before the device will accept the erase sector instruction (status register bit wel must equal 1). t he instruction is initiated by driving the /cs pin low and shifting the instruction code ?d8h? follow ed a 24-bit sector address (a23-a0) (see figure 2). the sector erase instruction sequence is shown in figure 11. the /cs pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the sector erase instruction w ill not be executed. after /cs is dr iven high, the self-timed sector erase instruction will commence for a time duration of t se (see ac characteristics). while the sector erase cycle is in progress, the read status register instruction may still be accessed for checking the status of the busy bit. the busy bit is a 1 duri ng the sector erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. after the sector erase cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. the sector erase instruction will not be exec uted if the addressed page is protec ted by the block protect (bp2, bp1, bp0) bits (see status regist er memory protection table). figure 11. sector erase instruction sequence diagram www.datasheet.co.kr datasheet pdf - http://www..net/
w25P80 and w25p16 - 22 - 9.2.11 chip erase (c7h) the chip erase instruction sets all memory within the device to the erased state of all 1s (ffh). a write enable instruction must be executed before the device will acc ept the chip erase instruction (status register bit wel must equal 1). the instru ction is initiated by driving the /cs pin low and shifting the instruction code ?c7h?. the chip er ase instruction sequence is shown in figure 12. the /cs pin must be driven high after the eighth bit has been latched. if this is not done the chip erase instruction will not be executed. after /cs is driven high, the self-timed chip erase instruction will commence for a time duration of t ce (see ac characteristics). while the chip erase cycle is in progress, the read status register instruction may still be accessed to check the status of the busy bit. the busy bit is a 1 during the chip erase cy cle and becomes a 0 when finished and the device is ready to accept other instructi ons again. after the chip erase cy cle has finished the write enable latch (wel) bit in the status register is cleared to 0. the chip erase instruction will not be executed if any page is protected by the block protect (bp2, bp1, bp0) bits (see status register memory protection table). figure 12. chip erase instruction sequence diagram www.datasheet.co.kr datasheet pdf - http://www..net/
w25P80 and w25p16 publication release date: september 22, 2006 - 23 - revision l 9.2.12 power-down (b9h) although the standby current during nor mal operation is relatively low, standby current can be further reduced with the power-down instruction. the lower power consumption makes the power-down instruction especially useful for battery pow ered applications (see icc1 and icc2 in ac characteristics). the instruction is initiated by driving the /cs pin low and shifting the instruction code ?b9h? as shown in figure 13. the /cs pin must be driven high after the eighth bit has been latched. if this is not done the power- down instruction will not be executed. after /cs is driven high, the power-down state will entered within the time duration of t dp (see ac characteristics). while in the power-down state only the release from power-down / device id instruction, which restores the device to normal operation, will be recognized. all other instructions are ignored. this includes the r ead status register instruction, which is always available during normal operation. ignoring all but one instruction makes the power down state a useful condition for securing maximum write protection. the device always powers-up in the normal operation with t he standby current of icc1. figure 13. deep power-down instruction sequence diagram 9.2.13 release power-down / device id (abh) the release from power-down / device id instructi on is a multi-purpose instruction. it can be used to release the device from the power- down state, obtain the devices elec tronic identification (id) number or do both. when used only to release the device from the power- down state, the instructi on is issued by driving the /cs pin low, shifting the instruction code ?abh ? and driving /cs high as shown in figure 14. after the time duration of t res1 (see ac characteristics) the devic e will resume normal operation and other instructions will be accepted. the /cs pin must remain high during the t res1 time duration. when used only to obtain the device id while not in the power-down state, the instruction is initiated by driving the /cs pin low and shifting the instru ction code ?abh? followed by 3-dummy bytes. the device id bits are then shifted out on the falling edge of clk with most significant bit (msb) first as shown in figure 15. the device id values for the w25P80 and w25p16 are listed in manufacturer and device identification table. the device id can be read continuously. the instruction is completed by driving /cs high. www.datasheet.co.kr datasheet pdf - http://www..net/
w25P80 and w25p16 - 24 - when used to release the device from the power-dow n state and obtain the devi ce id, the instruction is the same as previously described, and shown in figure 13, except that after /cs is driven high it must remain high for a time duration of t res2 (see ac characteristics). after this time duration the device will resume normal operation and ot her instructions will be accepted. if the release from power-down / device id instru ction is issued while an erase, program or write cycle is in process (when busy equals 1) the inst ruction is ignored and will not have any effects on the current cycle. figure 14. release power-down instruction sequence figure 15. release power-down / devi ce id instruction sequence diagram www.datasheet.co.kr datasheet pdf - http://www..net/
w25P80 and w25p16 publication release date: september 22, 2006 - 25 - revision l 9.2.14 read manufacturer / device id (90h) the read manufacturer/device id instruction is an alternative to the release from power-down / device id instruction that prov ides both the jedec assigned manufac turer id and the specific device id. the read manufacturer/device id instruction is very similar to the release from power-down / device id instruction. the instruction is initiated by driving the /cs pin low and shifting the instruction code ?90h? followed by a 24-bit address (a23-a0) of 000000h. after which, the manufacturer id for winbond (efh) and the device id are shifted out on the falling edge of clk with most significant bit (msb) first as shown in figure 16. the device id values for the w25P80 and w25p16 are listed in manufacturer and device identification table. if the 24-bit addre ss is initially set to 000001h the device id will be read first and then followed by the manufacturer id. the manufacturer and device ids can be read continuously, alternating from one to the other. the instruction is completed by driving /cs high. figure 16. read manufacturer / device id diagram www.datasheet.co.kr datasheet pdf - http://www..net/
w25P80 and w25p16 - 26 - 9.2.15 jedec id (9fh) for compatibility reasons, the w25P80/16 provides seve ral instructions to electronically determine the identity of the device. the read je dec id instruction is compatible with the jedec standard for spi compatible serial memories that was adopted in 2003. the instruction is initiated by driving the /cs pin low and shifting the instruction code ?9fh?. the jedec assigned manufacturer id byte for winbond (e fh) and two device id bytes, memory type (id15-id8) and capacity (id7-id0) are then shifted out on the falling edge of clk with most significant bit (msb) first as shown in figure 17. for the w25P80, the memory type is 20h and the capacity is 14h. for the w25p16, the memory ty pe is also 20h and the capacity is 15h. figure 17. read jedec id www.datasheet.co.kr datasheet pdf - http://www..net/
w25P80 and w25p16 publication release date: september 22, 2006 - 27 - revision l 9.2.16 read parameter page (53h) the parameter page is a 256-byte page of flash memo ry that can be used for storing serial numbers, revision information and configurat ion data that might typically be stored in an additional serial eeprom memory. because the parameter page is rela tively small and separate from the array, the erase time is significantly shorter than that of a sector erase (see t pe in ac electrical characteristics). this makes it convenient for more frequent updates. the read parameter page instruction allows one or more bytes of the parameter page to be read. the instruction is initiated by driving the /cs pin low and then shifting the instruction code ?53h? followed by a 24-bit address (a23-a0) into the di pin. only the lower 8 address bits (a7-a0) are used, the 16 upper most address bits (a23-a8) are ignored (don?t care). the code and address bits are latched on the rising edge of the clk pin. after t he address is received, the data byte of the addressed memory location will be shifted out on t he do pin at the falling edge of clk with most significant bit (msb) first. the address is automat ically incremented to the next higher address after each byte of data is shifted out allowing for a continuous stream of dat a. when the end of the parameter page is reached the address will wrap to the beginning. the read parameter page instruction is shown in figure 18. if the read para meter page instruction is issued while an erase, program or write cycle is in process (busy=1) t he instruction is ignored and will not have any effects on the current cycle. the read parameter page inst ruction allows clock rates from d.c. to a maximum of f r (see ac electrical characteristics). figure 18. read parameter page instruction sequence diagram www.datasheet.co.kr datasheet pdf - http://www..net/
w25P80 and w25p16 - 28 - 9.2.17 fast read parameter page (5bh) the fast read parameter page instruction is bas ically the same as the read parameter page instruction except that it allows for a faster clock rate to be used. the fast read parameter page instruction can opperate at clock rate s from d.c. to a maximum of f r (see ac electrical characteristics). this is accomplished by adding a ? dummy? byte after the 24-bit address, as shown in figure 19. the dummy byte allows the devices inter nal circuits additional time for setting up the initial address. the dummy byte data value on the di pin is a ?don?t care?. figure 19. fast read parameter page instruction sequence diagram www.datasheet.co.kr datasheet pdf - http://www..net/
w25P80 and w25p16 publication release date: september 22, 2006 - 29 - revision l 9.2.18 program parameter page (52h) the program parameter page instruction allows up to 256 bytes (128 words) to be programmed at memory word locations that have been previously erased to all 1s ?ffffh? (see erase parameter page instruction). a write enable instruction mu st be executed before the device will accept the program parameter page instruction (status regist er bit wel must equal 1). the instruction is initiated by driving the /cs pin low then shifting t he instruction code ?52h? followed by a 24-bit address (a23-a0) and the full 256 data bytes, into the di pin. only the lower 8 address bits (a7-a0) are used, the 16 upper most address bit (a23-a8) are ignored (don?t care). because the w25P80/16 programs in increments of one word (two bytes) at a ti me, the address must be an even address (a0 must equal 0). the /cs pin must be held low for the entire length of the instruction while data is being sent to the device. the program parameter page inst ruction sequence is shown in figure 20. the start address of the needs to be set to 00h on the parameter page. if more than 256 bytes are sent to the device the addressing will wrap to t he beginning of the page. if pr eviously written data bytes are over-written the data will not be valid. in most applications it is best to read the full 256-byte contents of the page into a temporary ram. data can then be modified as needed and the entire 256 bytes can then be reprogrammed into the parameter page at one time. as with the write and erase instructions, the /cs pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the pa rameter page program instruction will not be executed. after /cs is driven high, the self-timed page program inst ruction will commence for a time duration of t pp (see ac characteristics). while the page program cycle is in progress, the read status register instruction may still be accessed for checking the status of the busy bit. the busy bit is a 1 during the program cycle and becomes a 0 when the cycle is finis hed and the device is ready to accept other instructions agai n. after the program cycle has fi nished the write enable latch (wel) bit in the status register is cleared to 0. the program parameter page instruction will not be executed if the addressed page is protected by the block pr otect (bp2, bp1, bp0) bits (see status register memory protection table). www.datasheet.co.kr datasheet pdf - http://www..net/
w25P80 and w25p16 - 30 - figure 20. parameter page program instruction sequence diagram www.datasheet.co.kr datasheet pdf - http://www..net/
w25P80 and w25p16 publication release date: september 22, 2006 - 31 - revision l 9.2.19 erase parameter page (d5h) the erase parameter page instruction sets all 256 bytes of memory in the parameter page to the erased state of all 1s (ffh). a write enable instru ction must be executed befor e the device will accept the erase parameter page instruction (status regi ster bit wel must equal 1). the instruction is initiated by driving the /cs pin low and shifting t he instruction code ?d5h?. the erase parameter page instruction sequence is shown in figure 21. the /cs pin must be driven high after the eighth bit has been latched. if this is not done the erase parameter page instruction will not be executed. after /cs is driven high, the self-timed erase parameter page instruction will commence for a time duration of t pe (see ac characteristics). while the erase parameter page cycle is in progress, the read status register instruction may still be accessed to check the status of the busy bit. t he busy bit is a 1 during the erase parameter page cycle and becomes a 0 when finished and the device is r eady to accept other in structions again. after the erase parameter page cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. the erase parameter page instruct ion will not be executed if any page is protected by the block protect (bp2, bp1, bp0) bits (see st atus register memory protection table). figure 21. parameter page erase instruction sequence diagram www.datasheet.co.kr datasheet pdf - http://www..net/
w25P80 and w25p16 - 32 - 10. electrical characteristics 10.1 absolute maximum ratings (1) parameters symbol conditions range unit supply voltage vcc ?0.6 to +4.0 v voltage applied to any pin v io relative to ground ?0.6 to vcc +0.4 v storage temperature t stg ?65 to +150 c lead temperature t lead see note 2 c electrostatic discharge voltage v esd human body model (3) ?2000 to +2000 v notes: 1. this device has been designed and tested fo r the specified operation ranges. proper oper ation outside of these levels is not guaranteed. exposure beyond absolute maximum ratings (listed above) may cause permanent damage. 2. compliant with jedec standard j-std-20c for small body sn -pb or pb-free (green) assembly and the european directive on restrictions on hazardous s ubstances (rohs) 2002/95/eu. 3. jedec std jesd22-a114a (c1=100 pf, r1=1500 ohms, r2=500 ohms). 10.2 operating ranges spec parameter symbol conditions min max unit supply voltage (1) vcc f r = 33mhz, f r = 25mhz f r = 50mhz, f r = 25mhz 2.7 3.0 3.6 3.6 v v ambient temperature, operating t a industrial ?40 +85 c note: 1. vcc voltage during read can operate across the min and ma x range but should not exceed 10% of the programming (erase/write) voltage. www.datasheet.co.kr datasheet pdf - http://www..net/
w25P80 and w25p16 publication release date: september 22, 2006 - 33 - revision l 10.3 power-up timing and write inhibit threshold spec parameter symbol min max unit vcc (min) to /cs low t vsl (1) 10 s time delay before write instruction t puw (1) 1 10 ms write inhibit threshold voltage v wi (1) 1 2 v note: 1. these parameters are characterized only. figure 22. power-up timing and voltage levels www.datasheet.co.kr datasheet pdf - http://www..net/
w25P80 and w25p16 - 34 - 10.4 dc electrical characteristics (preliminary) (1) spec parameter symbol conditions min typ max unit input capacitance c in (2) v in = 0v (2) 6 pf output capacitance cout (2) v out = 0v (2) 8 pf input leakage i li 2 a i/o leakage i lo 2 a standby current i cc 1 /cs = vcc, vin = gnd or vcc 25 50 a power-down current i cc 2 /cs = vcc, vin = gnd or vcc <1 5 a current read data 1mhz (3) i cc 3 c = 0.1 vcc / 0.9 vcc do = open 4 8 ma current read data 20mhz (3) c = 0.1 vcc / 0.9 vcc do = open 8 12 ma current read data 33mhz (3) c = 0.1 vcc / 0.9 vcc do = open 9 15 ma current page program i cc 4 /cs = vcc 23 27 ma current write status register i cc 5 /cs = vcc 10 15 ma current sector erase i cc 6 /cs = vcc 23 27 ma current chip erase i cc 7 /cs = vcc 23 27 ma input low voltage v il ?0.5 vcc x0.3 v input high voltage v ih vcc x0.7 vcc +0.4 v output low voltage v ol i ol = 1.6 ma 0.4 v output high voltage v oh i oh = ?100 a vcc ?0.2 v notes: 1 .see preliminary designation. 2. tested on sample basis and specified through desi gn and characterization data. ta=25 c, vcc 3v 3. checker board pattern. www.datasheet.co.kr datasheet pdf - http://www..net/
w25P80 and w25p16 publication release date: september 22, 2006 - 35 - revision l 10.5 ac measurement conditions spec parameter symbol min max unit load capacitance c l 30 30 pf input rise and fall times t r , t f 5 ns input pulse voltages v in 0.2 vcc to 0.8 vcc v output timing reference voltages o ut 0.3 vcc to 0.7 vcc v note: 1. output hi-z is defined as the poi nt where data out is no longer driven. figure 23. ac measurement i/o waveform www.datasheet.co.kr datasheet pdf - http://www..net/
w25P80 and w25p16 - 36 - 10.6 ac electrical characteristics spec description symbol alt min typ max unit clock frequency, for fast read (0bh) and all other instructions except read data (03h) 2.7v-3.6v vcc 3.0v-3.6v vcc f r f c d.c. d.c. 33 50 mhz mhz clock freq. read data instruction 03h f r d.c. 25 mhz clock high, low time, for fast read (0bh) and all other instructions except read data (03h) t clh , t cll (1) 9 ns clock high, low time for read data instruction t crlh , t crll (1) 9 ns clock rise time peak to peak t clch (2) 0.1 v/ns clock fall time peak to peak t chcl (2) 0.1 v/ns /cs active setup time relative to clk t slch t css 5 ns /cs not active hold time relative to clk t chsl 5 ns data in setup time t dvch t dsu 2 ns data in hold time t chdx t dh 5 ns /cs active hold time relative to clk (2.7v-3.6v / 3.0v-3.6v) t chsh 10/8 ns /cs not active setup time relative to clk t shch 5 ns /cs deselect time t shsl t csh 100 ns output disable time (2.7v-3.6v / 3.0v-3.6v) t shqz (2) t dis 12/10 ns clock low to output valid (2.7v-3.6v / 3.0v-3.6v) t clqv t v 12/8 ns output hold time t clqx t ho 0 ns /hold active setup time relative to clk (2.7v-3.6v / 3.0v-3.6v) t hlch 5 ns /hold active hold time relative to clk tchhh 5 ns www.datasheet.co.kr datasheet pdf - http://www..net/
w25P80 and w25p16 publication release date: september 22, 2006 - 37 - revision l ac electrical characteristics, continued spec description symbol alt min typ max unit /hold not active setup time relative to clk t hhch 5 ns /hold not active hold time relative to clk t chhl 5 ns /hold to output low-z t hhqx (2) t lz 9 ns /hold to output high-z t hlqz (2) t hz 9 ns write protect setup time before /cs low t whsl (4) 20 ns write protect hold time after /cs high t shwl (4) 100 ns /cs high to power-down mode t dp (2) 3 s /cs high to standby mode without electronic signature read t res 1 (2) 30 s /cs high to standby mode with electronic signature read t res 2 (2) 30 s write status register cycle time t w 17 25 ms page program cycle time (5) 3.0v-3.6v vcc 2.7v-3.6v vcc t pp 3.5 4 7 8 ms ms sector erase cycle time t se 0.6 1.5 s chip erase cycle time w25P80 chip erase cycle time w25p16 t ce 7 12 15 25 s s parameter page erase cycle time t pe 100 200 ms notes: 1. clock high + clock low must be less than or equal to 1/f c . 2. value guaranteed by design and/or charac terization, not 100% tested in production. 3. expressed as a slew-rate. 4. only applicable as a constraint for a write status register instruction w hen sector protect bit is set at 1. 5. maximum tpp uses worse-case user pattern at 85c. www.datasheet.co.kr datasheet pdf - http://www..net/
w25P80 and w25p16 - 38 - 10.7 serial output timing 10.8 input timing 10.9 hold timing www.datasheet.co.kr datasheet pdf - http://www..net/
w25P80 and w25p16 publication release date: september 22, 2006 - 39 - revision l 11. package specification 11.1 8-pin soic 208-mil (winbond package code ss) millimeters inches symbol min max min max a 1.75 2.16 0.069 0.085 a1 0.05 0.25 0.002 0.010 a2 1.70 1.91 0.067 0.075 b 0.35 0.48 0.014 0.019 c 0.19 0.25 0.007 0.010 d 5.18 5.38 0.204 0.212 e 7.70 8.10 0.303 0.319 e1 5.18 5.38 0.204 0.212 e 1.27 bsc 0.050 bsc l 0.50 0.80 0.020 0.031 0 o 8 o 0 o 8 o y --- 0.10 --- 0.004 notes: 1. controlling dimensions: inches , unless otherwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d and e1 do not include mold flash protrusi ons and should be measured from the bottom of the package. www.datasheet.co.kr datasheet pdf - http://www..net/
w25P80 and w25p16 - 40 - 11.2 16-pin soic 300-mil (winbond package code sf) millimeters inches symbol min max min max a 2.36 2.64 0.093 0.104 a1 0.10 0.30 0.004 0.012 b 0.33 0.51 0.013 0.020 c 0.18 0.28 0.007 0.011 d (3) 10.08 10.49 0.397 0.413 e 10.01 10.64 0.394 0.419 e1 (3) 7.39 7.59 0.291 0.299 e (2) 1.27 bsc 0.050 bsc l 0.39 1.27 0.015 0.050 0 o 8 o 0 o 8 o y --- 0.076 --- 0.003 notes: 1. controlling dimensions: inches , unless otherwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d and e1 do not include mold flash protrusi ons and should be measured from the bottom of the package. www.datasheet.co.kr datasheet pdf - http://www..net/
w25P80 and w25p16 publication release date: september 22, 2006 - 41 - revision l 12. ordering information (3) 1. the winbond w25P80/16 are fully compatible with the prev ious nexflash nx25P80/16 seri al flash memories. the ?w? prefix is not included on the part marking. 2. only the second letter is used for part marking. 3. standard bulk shipments are in tube (shape e). please s pecify alternate packing method, such as tape and reel (shape t), when placing orders www.datasheet.co.kr datasheet pdf - http://www..net/
w25P80 and w25p16 - 42 - 13. revision history version date page description a 03/05/04 new create b 03/24/04 mlp metal die pad notification; under "package types," figure 1 and packaging information. c 04/19/04 corrected timing diagrams for figure 16 (read manufacturer / device id diagram) and figure 17 (read jedec id). added 8x6mm mlp package for w25p16. d 05/06/04 corrected dimensions in packaging information section for 6x5mm and 8x6mm mlp. e 06/28/04 changed 200-mil soic reference to 208-mil soic. updated dimensional table for the 208milsoic in the packaging information. added 208milsoic and removed 5x6mm mlp for w25p16. f 10/07/04 added parameter page data to features, block diagram (figure 2), status register memory protection, instruction set and manufacturer and device identification. added parameter page timing diagrams (figures 20, 21, 22 and 23). updated f r , t ch and t pe data in ac electrical characteristics g 04/22/05 updated ac and dc parameters and package type descriptions. removed 8-contact 6x5 and 8x6 mlp packages from document. corrected data in instruction set. updated package dimension symbols for compliance. h 06/14/05 updated important notice i 06/28/05 changed nexflash part numbers to winbond part numbers and updated ordering and contact information j 12/11/05 all updated data sheet to comply with winbond standard. updated fr and f r values in operating ranges table and ac characteristics table. updated read data (f r ) values in operating range and ac characteristics tables from 33mhz to 25mhz. corrected the pin assignment on table of pin description of page 5. k 08/01/06 all removed 25p32, see 25x32 data sheet for 32mb density updated icc1 to icc 7 specs. l 09/22/06 15 & 41 corrected write enable/disable text. added footnotes in the order ing information table. www.datasheet.co.kr datasheet pdf - http://www..net/
w25P80 and w25p16 publication release date: september 22, 2006 - 43 - revision l preliminary designation the ?preliminary? designation on a winbond data sheet indicates that the product is not fully characterized. the specifications are subject to change and are not g ua ranteed. winbond or an authorized sales representative should be consulted fo r current information before using this product. trademarks winbond and spiflash are trademarks of winbond electronics corporation all other marks are the property of their respective owner. important notice winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgi cal implantation, atomic energy control instruments, airplane or spaceship instrument s, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. further more, winbond products are not intended for applications wherein failure of winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sales. the winbond w25P80/16 are fully compatible with t he previous nexflash nx25P80/16 serial flash memories. www.datasheet.co.kr datasheet pdf - http://www..net/

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